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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13709-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90580B Series
MB90583B/587/F583B/V580B
s DESCRIPTION
The MB90580B series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90580B series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90580B has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90580B series include: an 8/10-bit A/D converter, an 8-bit D/A converter, UARTs (SCI) 0 to 4, an 8/16-bit PPG timer, 16-bit I/O timers (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 1), and an IEBusTM controller *2. Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. *2: IEBusTM is a trademark of NEC Corporation.
s FEATURES
* Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 * Maximum memory space 16 Mbyte Linear/bank access (Continued)
s PACKAGES
100 pin plastic LQFP 100 pin plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90580B Series
(Continued) * Instruction set optimized for controller applications Supported data types: bit, byte, word, and long-word types Standard addressing modes: 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions * Enhanced high level language (C) and multitasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed: 4 byte instruction queue * Enhanced interrupt function Up to eight priority levels programmable External interrupt inputs: 8 lines * Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs: 8 lines * Internal ROM FLASH: 128 Kbyte MASKROM: 128 Kbyte (MB90583B) , 64 Kbyte (MB90587) * Internal RAM FLASH: 6 Kbyte MASKROM: 6 Kbyte (MB90583B) , 4 Kbyte (MB90587) * General-purpose ports Up to 77 channels (Input pull-up resistor settable for: 24 channels. Output open drain settable for: 8 channels) * IEBusTM controller* Three different data transfer rates selectable Mode 0: 3.9 Kbps (16 bytes/frame) Mode 1: 17.0 Kbps (32 bytes/frame) Mode 2: 26.0 Kbps (128 bytes/frame) *: IEBusTM is a trademark of NEC Corporation. * A/D Converter (RC) : 8 ch 8/10-bit resolution Conversion time: 34.7 s (Min.) , 12 MHz operation * D/A Converter: 2 ch 8-bit resolutions Setup time: 12.5 s * UART : 5 ch * 8/16 bit PPG : 1 ch 8 bits x 2 channels: 16 bits x 1 channel: Mode switching function provided * 16 bit reload timer: 3 ch * 16-bit PWC timer: 1 channel Noise filter provided. Available to pulse width counter * 16 bit I/O timer Input capture : 4 ch Output compare : 2 ch Free run timer: 1 ch * Internal clock generator * Time-base counter/watchdog timer: 18-bit (Continued)
2
MB90580B Series
(Continued) * Clock monitor function integrated * Low-power consumption mode Sleep mode Stop mode Hardware standby mode CPU intermittent operation mode * Package: LQFP-100 / QFP-100 * CMOS technology
3
MB90580B Series
s PRODUCT LINEUP
Part number Item Classification ROM size RAM size Emulator-specific power supply *1 MB90587 MB90583B MB90F583B Mass-produced products (Flash ROM) 128 Kbytes 6 Kbytes MB90V580B Development/ evaluation product None 6 Kbytes None
Mass-produced products (MASK ROM) 64 Kbytes 4 Kbytes 128 Kbytes 6 Kbytes
CPU functions
The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output) General-purpose I/O port (Can be set as open-drain) General-purpose I/O ports (Input pull-up resistors available) Total: : 45 :8 : 24 : 77
Ports
IEBusTM controller
None
Communication mode: Half-duplex, asynchronous communication Multi-master system Access control: CDMA/CD Three modes selectable for different transmission speeds Transmit buffer: 8-byte FIFO buffer Receive buffer: 8-byte FIFO buffer
Timebase timer Watchdog timer Clock timer
18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (At oscillation of 4 MHz) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) 15-bit counter Interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (At oscillation of 32.768 kHz) Number of channels: 1 (8-bit x 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 3 Event count provided Interval: 125 ns to 131 ms (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 1 Timer function (select the counter timer from three internal clocks.) Pulse width measuring function (select the counter timer from three internal clocks.)
8/16-bit PPG timer
16-bit reload timer
PWC timer
(Continued)
4
MB90580B Series
(Continued)
Part number Item 16-bit free run timer 16-bit I/O timer Output compare (OCU) Input capture (ICU) MB90587 Number of channels: 1 Overflow interrupts Number of channels: 2 Pin input factor: A match signal of compare register Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) MB90583B MB90F583B MB90V580B
Number of inputs: 8 DTP/external interrupt circuit Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Delayed interrupt generation module An interrupt generation module for switching tasks used in real time operating systems. Clock synchronized transmission (62.5 Kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. Resolution: 8/10-bit changeable Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel repeatedly) Stop conversion mode (converts selected channel and stop operation repeatedly) 8-bit resolution Number of channels: 2 channels Based on the R-2R system Sleep/stop/CPU intermittent operation/clock timer/hardware standby CMOS 4.5 V to 5.5 V *2
UART0, 1, 2, 3, 4
A/D converter
D/A converter Low-power consumption (standby) mode Process Power supply voltage for operation*
*1 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2 : Varies with conditions such as the operating frequency (See section "s ELECTRICAL CHARACTERISTICS"). Assurance for the MB90V580B is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 C, and an operating frequency of 1 MHz to 16 MHz.
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-100P-M05 FTP-100P-M06 : Available x: Not available 5 MB90583B MB90587 MB90F583B
Note: For more information about each package, see section "s PACKAGE DIMENSIONS".
MB90580B Series
s DIFFERENCES AMONG PRODUCTS
Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V580B does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V580B, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) * In the MB90583B/587/F583B, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. IEBusTM Controller * MB90587 does not have an IEBusTM Controller.
6
MB90580B Series
s PIN ASSIGNMENT
(TOP VIEW)
100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA2 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RST PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX* TX* P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2
P71 P72 DVRH DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 HST
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
* : N.C. pin on the MB90587
(FPT-100P-M05)
7
MB90580B Series
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 C P71 P72 DVRH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X0A X1A PA2 RST PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX* TX* P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 HST MD2
8
DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
* : N.C. pin on the MB90587
(FPT-100P-M06)
MB90580B Series
s PIN DESCRIPTION
Pin no. QFP*1 82 83 52 77 LQFP*2 80 81 50 75 Pin name X0 X1 HST RST P00 to P07 AD00 to AD07 P10 to P17 AD08 to AD15 P20 to P27 A16 to A23 P30 9 7 ALE P31 RD P32 12 10 WRL Circuit type A A C B Oscillator pin Oscillator pin Hardware standby input pin Reset input pin Function
85 to 92 83 to 90
General-purpose I/O ports. A pull-up resistor can be assigned (RD07 to RD00="1") by the pullup resistor setting register (RDR0). [These pins are disabled with D (CMOS/H) the output setting (DDR0 register: D07 to D00="1").] In external bus mode, the pins function as the lower data I/O or lower address outputs (AD00 to AD07). General-purpose I/O ports. A pull-up resistor can be assigned (RD17 to RD10="1") by the pullup resistor setting register (RDR1). [These pins are disabled with F (CMOS/H) the output setting (DDR1 register: D17 to D10 ="1").] In 16-bit external bus mode, the pins function as the upper data I/O or middle address outputs (AD08 to AD15). General-purpose I/O ports In external bus mode, pins for which the corresponding bit in the HACR register is "1" function as the A16 to A23 pins.
93 to 100
91 to 98
1 to 8
99,100, 1 to 6
F (CMOS/H) In external bus mode, pins for which the corresponding bit in the HACR register is "1" function as the upper address output pins (A16 to A23). F (CMOS/H) Functions as the address latch enable signal pin (ALE) in external bus mode. General-purpose I/O port F Functions as the RD pin in external bus mode. (CMOS/H) Functions as the read strobe output pin (RD) in external bus mode. General-purpose I/O port Functions as the WRL pin in external bus mode if the WRE bit is "1". Functions as the lower data write strobe output pin (WRL) in external bus mode. General-purpose I/O port Functions as the WRH pin in 16-bit external bus mode if the WRE bit in the EPCR register is "1" Functions as the upper data write strobe output pin (WRH) in external bus mode. General-purpose I/O port Functions as the ALE pin in external bus mode.
10
8
F (CMOS/H)
P33 13 11 WRH *1: FPT-100P-M06 *2: FPT-100P-M05
F (CMOS/H)
(Continued)
9
MB90580B Series
Pin no. QFP*
1
LQFP*
2
Pin name
Circuit type
Function
14
12
P34 HRQ P35
General-purpose I/O port Functions as the HRQ pin in external bus mode if the HDE bit in the F (CMOS/H) EPCR register is "1". Functions as the hold request input pin (HRQ) in external bus mode. General-purpose I/O port Functions as the HAK pin in external bus mode if the HDE bit in the EPCR register is "1". Functions as the hold acknowledge output pin (HAK) in external bus mode.
15
13 HAK
F (CMOS/H)
16
14
P36 RDY P37
General-purpose I/O port Functions as the RDY pin in external bus mode if the RYE bit in the F (CMOS/H) EPCR register is "1". Functions as the external ready input pin (RDY) in external bus mode. General-purpose I/O port Functions as the CLK pin in external bus mode if the CKE bit in the EPCR register is "1". Functions as the machine cycle clock output pin (CLK) in external bus mode. General-purpose I/O port. This pin serves as an open-drain output port with OD40 in the opendrain control setting register (ODR4) set to "1". [The pin is disabled with the input setting (DDR4 register: D40="0").]
17
15 CLK
F (CMOS/H)
P40 18 16 SIN0
E (CMOS/H) UART0 serial data input (SIN0) pin. When UART0 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally.
P41 19 17 SOT0
General-purpose I/O port. This pin serves as an open-drain output port with OD41 in the opendrain control setting register (ODR4) set to "1". [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D41="0").] UART0 serial data output pin (SOT0). This pin is enabled with the UART0 serial data output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD42 in the opendrain control setting register (ODR4) set to "1". [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D42="0").] UART0 serial clock I/O pin (SCK0). This pin is enabled with the UART0 clock output enabled.
P42 20 18 SCK0 *1: FPT-100P-M06 *2: FPT-100P-M05
(Continued)
10
MB90580B Series
Pin no. QFP*
1
LQFP*
2
Pin name
Circuit type
Function General-purpose I/O port. This pin serves as an open-drain output port with OD43 in the opendrain control setting register (ODR4) set to "1". [The pin is disabled with the input setting (DDR4 register: D43="0").]
P43 21 19 SIN1
E (CMOS/H) UART1 serial data input (SIN1) pin. When UART1 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally.
P44 22 20 SOT1
General-purpose I/O port. This pin serves as an open-drain output port with OD44 in the opendrain control setting register (ODR4) set to "1". [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D44="0").] UART1 serial data output pin (SOT1). This pin is enabled with the UART1 serial data output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD45 in the opendrain control setting register (ODR4) set to "1". [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D45="0").] UART1 serial clock I/O pin (SCK1). This pin is enabled with the UART1 clock output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD46 in the openE drain control setting register (ODR4) set to "1". [The pin is disabled (CMOS/H) with the input setting (DDR4 register: D46="0").] External trigger input pin (ADTG) for the A/D converter. General-purpose I/O port. E This pin serves as an open-drain output port with OD47 in the open(CMOS/H) drain control setting register (ODR4) set to "1". [The pin is disabled with the input setting (DDR4 register: D47="0").] General-purpose I/O port. Analog input pin (AN0) for use during A/D converter operation. G UART3 serial data input pin (SIN3). (CMOS/H) When UART3 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. G Analog input pin (AN1) for use during A/D converter operation. (CMOS/H) UART3 serial data output pin (SOT3). This pin is enabled with the UART3 serial data output enabled.
P45 24 22 SCK1
25
23
P46
ADTG
26
24
P47
P50 AN0 38 36 SIN3
P51 39 37 AN1 SOT3 *1: FPT-100P-M06 *2: FPT-100P-M05
(Continued)
11
MB90580B Series
Pin no. QFP*1 LQFP*2
Pin name Circuit type P52 General-purpose I/O port. G (CMOS/H)
Function
40
38
AN2 SCK3
Analog input pin (AN2) for use during A/D converter operation. UART3 serial clock I/O pin (SCK3). This pin is enabled with the UART3 clock output enabled. General-purpose I/O port. Analog input pin (AN3) for use during A/D converter operation. General-purpose I/O port. Analog input pin (AN4) for use during A/D converter operation.
41
39
P53 AN3 P54 AN4
G (CMOS/H)
43
41 SIN4
G (CMOS/H)
UART4 serial data input pin (SIN4). When UART4 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. Analog input pin (AN5) for use during A/D converter operation. UART4 serial data output pin (SOT4). This pin is enabled with the UART4 serial data output enabled. General-purpose I/O port. Analog input pin (AN6) for use during A/D converter operation. UART4 serial clock output pin (SCK4). This pin is enabled with the UART4 clock output enabled. General-purpose I/O port. Analog input pin (AN7) for use during A/D converter operation. 0.1 F capacitor coupling pin for regulating the power supply. General-purpose I/O port. General-purpose I/O port. This pin serves as a D/A output pin (DA00) when the DAE0 bit in the D/A control register (DACR) is "1". D/A converter output 0 (DA00) pin. General-purpose I/O port. This pin serves as a D/A output pin (DA01) when the DAE1 bit in the D/A control register (DACR) is "1". D/A converter output 1 pin (DA01). General-purpose I/O port. Functions as external interrupt request input 0 pin (IRQ0).
P55 44 42 AN5 SOT4 P56 45 43 AN6 SCK4 46 27 28 29 44 25 26 27 P57 AN7 C P71 P72 P73 DA00 P74 DA01 47 45 P80 IRQ0 F (CMOS/H) H (CMOS/H) G (CMOS/H) F (CMOS/H) G (CMOS/H) G (CMOS/H)
F (CMOS/H) General-purpose I/O port. H (CMOS/H)
32
30
33
31
*1: FPT-100P-M06 *2: FPT-100P-M05
(Continued)
12
MB90580B Series
Pin no. QFP*1 48 53 54 55 56 57 58 LQFP*2 46 51 52 53 54 55 56
Pin name Circuit type P81 IRQ1 P82 IRQ2 P83 IRQ3 P84 IRQ4 P85 IRQ5 P86 IRQ6 P87 IRQ7
Function
General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 1 pin (IRQ1). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 2 pin (IRQ2). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 3 pin (IRQ3). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 4 pin (IRQ4). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 5 pin (IRQ5). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 6 pin (IRQ6). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 7 pin (IRQ7). General-purpose I/O port. A pull-up resistor can be assigned (RD60="1") by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D60="1").]
P60 59 57 SIN2
D (CMOS/H) UART2 serial data input pin (SIN2). When UART2 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally.
P61 60 58 SOT2
General-purpose I/O port. A pull-up resistor can be assigned (RD61="1") by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting D (CMOS/H) (DDR6 register: D61="1").] UART2 serial data output pin (SOT2). This pin is enabled with the UART2 serial data output enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD62="1") by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting D (CMOS/H) (DDR6 register: D62="1").] UART2 serial clock I/O pin (SCK2). This pin is enabled with the UART2 clock output enabled.
P62 61 59 SCK2 *1: FPT-100P-M06 *2: FPT-100P-M05
(Continued)
13
MB90580B Series
(Continued)
Pin no. QFP*1 LQFP*2 Pin name Circuit type Function General-purpose I/O port. A pull-up resistor can be assigned (RD63="1") by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D63="1").] The pin serves as the PPG1 output when PPGs are enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD64="1") by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D64="1").] The pin serves as the PPG0 output when PPGs are enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD65="1") by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D65="1").] This pin serves as the CKOT output during CKOT operation. I J (CMOS) This pin serves as the IEBusTM output. This pin serves as the IEBusTM input. General-purpose I/O port. F (CMOS/H) Event input pins for reload timers 0, 1, and 2. During reload timer input, these inputs are used continuously and thus the output from any other function to the pins must be avoided unless used intentionally. Trigger inputs for input capture channels 0 to 2 General-purpose I/O port. F (CMOS/H) Reload timer output pin. This function is applied when the output for reload timer 0 is enabled. Trigger inputs for input capture channel 3. General-purpose I/O port. F (CMOS/H) Reload timer output pins. This function is applied when the output for reload timer 1 and 2 are enabled. Event output for channel 0 and 1 of the output compare General-purpose I/O port. This pin serves as the PWC input with the PWC timer enabled.
62
60
P63
D (CMOS/H)
PPG1
63
61
P64
D (CMOS/H)
PPG0
64
62
P65
D (CMOS/H)
CKOT 65 66 63 64 TX*3 RX*3 P90 to P92 67 to 69 65 to 67 TIN0 to TIN2 IN0 to IN2 P93 70 68 TOT0 IN3 P94, P95 71, 72 69, 70 TOT1, TOT2 OUT0, OUT1 73 71 P96 PWC F (CMOS/H)
*1: FPT-100P-M06 *2: FPT-100P-M05 *3: N.C. pin on the MB90587.
(Continued)
14
MB90580B Series
(Continued)
Pin no. QFP*1 74 75, 76 78 79 80 34 37 35 36 30 31 LQFP*2 72 73, 74 76 77 78 32 35 33 34 28 29 Pin name Circuit type P97 POT PA2 X1A X0A AVCC AVSS AVRH AVRL DVRH DVSS MD0 to MD2 VCC VSS F (CMOS/H) General-purpose I/O port. This pin serves as the PWC output with the PWC timer enabled. Function
PA0, PA1 F (CMOS/H) General-purpose I/O port. F (CMOS/H) General-purpose I/O port. A A C Oscillation input pin. Oscillation input pin. A/D converter power supply pin. A/D converter power supply pin. A/D converter external reference power supply pin. A/D converter external reference power supply pin. D/A converter external reference power supply pin. D/A converter power supply pin. Input pin for specifying the operation mode. Connect these pins directly to Vcc or Vss. Power supply (5 V) input pin. Power supply (0 V) input pin.
49 to 51 47 to 49 23, 84 11, 42, 81 21, 82 9, 40, 79
*1: FPT-100P-M06 *2: FPT-100P-M05
15
MB90580B Series
s I/O CIRCUIT TYPE
Type
X1, X1A
Circuit
Remarks * Oscillation feedback resistance : Approx. 1 M Clock input
X0, X0A
A
HARD,SOFT STANDBY CONTROL
* Hysteresis input with pull-up Resistance approx. 50 k B
* Hysteresis input C
Pull-up resistor control
* Incorporates pull-up resistor control (for input) * CMOS level output * Hysteresis input with standby control Resistance approx. 50 k
D
Standby control signal
(Continued)
16
MB90580B Series
Type
Circuit
Remarks * CMOS level output * Hysteresis input with standby control * Incorporates open-drain control
* Open-drain control signal
E
Standby control signal * CMOS level output * Hysteresis input with standby control
F
Standby control signal * CMOS level output * Hysteresis input with standby control * Analog input
G Analog input
Standby control signal
(Continued)
17
MB90580B Series
(Continued)
Type Circuit Remarks * CMOS level output * Hysteresis input with standby control * DA output
H DA output
Standby control signal * CMOS level output
I
* CMOS input with standby control J Standby control signal
18
MB90580B Series
s HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations: * When a voltage higher than Vcc or lower than Vss is applied to input or output pins. * When a voltage exceeding the rating is applied between Vcc and Vss. * When AVcc power is supplied prior to the Vcc voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage.
2. Handling unused input pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins.
3. Treatment of the TX and RX pins with the IEBusTM unused
When the IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down/pull-up resistor to the RX pin.
4. Use of the subclock mode and external clock
Even when the subclock mode is not used, connect an oscillator to the X0A or X1A pin. When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration below). MB90580B series
X0
Open
X1
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines.
19
MB90580B Series
It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device.
VCC VSS
VCC VSS VCC
VSS
MB90580B Series
VCC
VCC VSS
VSS
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of AVRH dose not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
9. Connection of Unused Pins of D/A Converter
Connect unused pin of D/A converter to DVRH = VSS, DVSS = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning,set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V).
20
MB90580B Series
12. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during a power-on reset after the power is turned on. Pay attention to the port output timing shown as follow. Oscillation settling time*2 Power-on reset*1
VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminate
*1: Power-on reset time: Period of "clock frequency x 217" (Clock frequency of 16 MHz: 8.192 ms) *2: Oscillation settling time: Period of "clock frequency x 218" (Clock frequency of 16 MHz: 16.384 ms)
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers turning on the power again.
14. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state.
15. Precautions for Use of 'DIV A, Ri,' and 'DIVW A, RWi' Instructions
The signed multiplication-division instructions 'DIV A, Ri,' and 'DIVW A, RWi' should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value '00h.' If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than '00h,' then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register.
16. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used. 21
MB90580B Series
s BLOCK DIAGRAM
X0, X1 X0A, X1A RST HST 6
Clock control circuit
RAM ROM
CPU Core of F2MC-16LX family Interrupt controller CMOS I/O port A I/O timer 16 bit ICU x 4 ch 16 bit OCU x 2 ch 16 bit free run timer 16 bit reload timer x 3 ch F2MC-16LX bus
3 3 PA0 to PA2 P90 to P92/ TIN0 to TIN2/ IN0 to IN2 P93/ TOT0/ IN3 2 P94, P95/ TOT1, TOT2/ OUT0, OUT1 P96/PWC P97/POT
P00 to P07/ AD00 to AD07 P10 to P17/ AD08 to AD15 P20 to P27/ A16 to A23 P30/ALE P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P47
8 8 8
CMOS I/O port 0 CMOS I/O port 1 CMOS I/O port 2 CMOS I/O port 3
Noise filter PWC timer 16 bit x 1 ch CMOS I/O port 9 Prescaler x 1 ch
Prescaler x 2 ch
CMOS I/O port 4
SIN0, SOT0, SCK0/ P40 to P42 SIN1, SOT1, SCK1/ P43 to P45
3 3
UART x 2 ch
UART x 1 ch 8 + 8 PPG x 1 ch 2 2 P63, P64/ PPG1, PPG0 P65/CKOT 3 SIN2, SOT2, SCK2/ P60 to P62 P80 to P87/ IRQ0 to IRQ7 P71, P72
Clock monitor
8
ADTG, P46 AVCC AVRH, AVRL AVSS SIN3, SOT3, SCK3/ P50 to P52/ AN0 to AN2
A/D converter (8/10 bit)
8
CMOS I/O port 6 External interrupt CMOS I/O port 8
8 2
Prescaler x 2 ch
CMOS I/O port 7 D/A converter (8 bit) x 2 ch
2 P73, P74 /DA00, DA01 DVRH DVSS
P53/AN3, P57/AN7 SIN4, SOT4, SCK4/ P54 to P56/ AN4 to AN6 TX RX
UART x 2 ch
CMOS I/O port 5
*
IEBusTM controller
Evaluation device (MB90V580B) This chip has no internal ROM. Internal RAM is 6 Kbytes. Internal resources are common. The package is PGA-256C-A02.
Other pins MOD2 to MOD0 C,VCC,VSS
P00 to 07 (8 channels): Provided with a register available as an input pull-up resistor. P10 to 17(8 channels): Provided with a register available as an input pull-up resistor. P60 to 65(6 channels): Provided with a register available as an input pull-up resistor. P40 to 47 (8 channels): Provided with a register available as an open drain. *: The MB90587 has no IEBusTM controller. The TX and RX pins are N.C. pins.
22
MB90580B Series
s MEMORY MAP
FFFFFFH
ROM area Address#1
FC0000H
ROM area
010000H
Address#2
ROM area (image of bank FF)
ROM area (image of bank FF)
004000H 002000H
: Internal : External
RAM
Register
Address#3
RAM
Register
RAM
Register
: Inhibited
000100H 0000C0H 000000H
Peripheral
Single chip mode A mirror function is supported
Peripheral Internal ROM external bus mode A mirror function is supported
Peripheral External ROM external bus mode
Parts No. MB90583B MB90F583B MB90587 MB90V580B
Address#1 FE0000H FE0000H FF0000H (FE0000H)
Address#2 004000H 004000H 004000H 004000H
Address#3 001900H 001900H 001100H 001900H
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
23
MB90580B Series
s F2MC-16LX CPU PROGRAMMING MODEL
* Dedicated registers
AH
AL
USP
: Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional data space.
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bit 16 bit 32 bit
24
MB90580B Series
* General-purpose registers
Maximum of 32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4
RL1 RW2 RW1 RL0 000180H + (RP x 10H) RW0 16 bit
* Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 I 0 S 1 T X N X Z X V X C X
Initial value
: Unused X : Undefined
25
MB90580B Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH to 1FH 20H 21H 22H 23H Serial mode register 0 Serial control register 0 Serial input data register 0/ serial output data register 0 Serial status register 0 SMR0 SCR0 SIDR0/ SODR0 SSR0 Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 output pin register Port 5 analog input enable register DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 ADER Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Abbreviated register Read/write name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W UART0 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 - 0 0B Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 Port 4, A/D 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
- - -0000-
B
Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 1 1 1 1 1 1 1 1B XXXXXXXXB
- - - XXXX -B
XXXXXXXXB XXXXXXXXB
- - - - - XXXB
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
- - - - - 0 0 0B
0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B
(Continued)
26
MB90580B Series
Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
Register name Serial mode register 1 Serial control register 1 Serial input data register 1/ serial output data register 1 Serial status register 1 Serial mode register 2 Serial control register 2 Serial input data register 2/ serial output data register 2 Serial status register 2 Clock division control register 0
Abbreviated register name SMR1 SCR1 SIDR1/ SODR1 SSR1 SMR2 SCR2 SIDR2/ SODR2 SSR2 CDCR0
Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
UART1
XXXXXXXXB 0 0 0 0 1 - 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
UART2
XXXXXXXXB 0 0 0 0 1 - 0 0B
Communications prescaler 0 Communications prescaler 1
0 - - - 1 1 1 1B
(Disabled) Clock division control register 1 CDCR1 R/W 0 - - - 1 1 1 1B
(Disabled) DTP/interrupt enable register DTP/interrupt factor register Request level setting register lower Request level setting register upper Clock division control register 2 ENIR EIRR R/W R/W DTP/external interrupt ELVR R/W 0 0 0 0 0 0 0 0B CDCR2 R/W Communications prescaler 2 0 - - - 1 1 1 1B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B
(Disabled) Control status register lower Control status register upper Data register lower Data register upper D/A converter data register 0 D/A converter data register 1 D/A control register 0 D/A control register 1 Clock output enable register ADCS1 ADCS2 ADCR1 ADCR2 DAT0 DAT1 DACR0 DACR1 CLKR R/W R/W R R or W R/W R/W R/W R/W R/W (Disabled) Clock monitor function D/A converter A/D converter 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 - XXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
- - - - - - - 0B - - - - - - - 0B - - - - 0 0 0 0B
(Continued)
27
MB90580B Series
Address 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H
Register name Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload register H (ch.1) PPG0 operating mode control register PPG1 operating mode control register PPG0 and 1 operating output control registers Timer control status register lower Timer control status register upper 16 bit timer register lower/ 16 bit reload register lower 16 bit timer register upper/ 16 bit reload register upper Timer control status register lower Timer control status register upper 16bit timer register lower/ 16 bit reload register lower 16 bit timer register upper/ 16 bit reload register upper Timer control status register lower Timer control status register upper 16 bit timer register lower/ 16 bit reload register lower 16 bit timer register upper/ 16 bit reload register upper PWC control status register lower PWC control status register upper PWC data buffer register lower PWC data buffer register upper Divide ratio control register
Abbreviated Read/ register write name PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGOE R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
8/16 bit PPG0/1
0 X 0 0 0 X X 1B 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B
(Disabled) TMCSR0 R/W 16 bit reload timer 0 R/W XXXXXXXXB R/W 16 bit reload timer 1 R/W XXXXXXXXB R/W 16 bit reload timer 2 R/W XXXXXXXXB R/W R/W R/W 16 bit PWC timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB
- - - - - - 0 0B
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
TMR0/ TMRLR0
XXXXXXXXB
TMCSR1
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
TMR1/ TMRLR1
XXXXXXXXB
TMCSR2
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
TMR2/ TMRLR2
XXXXXXXXB
PWCSR PWCR DIVR
(Disabled)
(Continued)
28
MB90580B Series
Abbreviated register Read/write name OCCP0 OCCP1 OCS0 OCS1 IPCP0 IPCP1 IPCP2 IPCP3 ICS01 R/W R/W R/W R/W R R R R R/W
Address 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H
Register name Compare register lower Compare register upper Compare register lower Compare register upper Compare control status register 0 Compare control status register 1 Input capture register lower Input capture register upper Input capture register lower Input capture register upper Input capture register lower Input capture register upper Input capture register lower Input capture register upper Input capture control status register 01 Input capture control status register 23 Timer data register lower Timer data register upper Timer control status register ROM mirroring function selection register Local-office address setting register L Local-office address setting register H Slave address setting register L Slave address setting register H Message length bit setting register Broadcast control bit setting register
Resource name Output compare (ch.0) Output compare (ch.1) Output compare (ch.0) Output compare (ch.1) Input capture (ch.0) Input capture (ch.1) Input capture (ch.2) Input capture (ch.3) Input capture (ch.0, ch.1) Input capture (ch.2, ch.3)
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B
(Disabled) ICS23 R/W 0 0 0 0 0 0 0 0B
(Disabled) TCDTL TCDTH TCCS ROMM MAWL MAWH SAWL SAWH DEWR DCWR R/W R/W R/W W R/W R/W R/W R/W R/W R/W IEBusTM controller Free-run timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B ROM mirror function - - - - - - - 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
(Continued)
29
MB90580B Series
Address 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H to 9DH
Register name Command register L Command register H Status register L Status register H Lock read register L Lock read register H Master address read register L Master address read register H Message length bit read register Broadcast control bit read register Write data buffer Read data buffer Serial mode register 3 Serial control register 3 Serial input register 3/ serial output register 3 Serial status register 3 PWC noise filter register Clock division control register 3 Serial mode register 4 Serial control register 4 Serial input register 4/ serial output register 4 Serial status register 4 Port 0 input pull-up resistor setup register Port 1 input pull-up resistor setup register Port 6 input pull-up resistor setup register Clock division control register 4
Abbreviated register Read/write name CMRL CMRH STRL STRH LRRL LRRH MARL MARH DERR DCRR WDB RDB SMR3 SCR3 SIDR3/ SODR3 SSR3 RNCR CDCR3 SMR4 SCR4 SIDR4/ SODR4 SSR4 RDR0 RDR1 RDR6 CDCR4 R/W R/W R R/W R R/W or R R R R R W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 1 1 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 1 1 XXXXB 0 0 XX 0 0 0 0B XXXXXXXXB 1 1 1 0 XXXXB XXXXXXXXB 1 1 1 1 XXXXB XXXXXXXXB 0 0 0 XXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
IEBusTM controller
UART3
XXXXXXXXB 0 0 0 0 1 - 0 0B
PWC noisefilter Communications prescaler 3
- - - - - 0 0 0B
0 - - - 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
UART4
XXXXXXXXB 0 0 0 0 1 - 0 0B
Port 0 Port 1 Port 2 Communications prescaler 4
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 - - - 1 1 1 1B
(Disabled)
(Continued)
30
MB90580B Series
Address
Register name Program address detection control/ status register Delayed interrupt generation/release register Low-power consumption mode control register Clock selection register
Abbreviated register name PACSR DIRR LPMCR CKSCR
Read/ write R/W R/W R/W or W R/W or R
Resource name Address match detection function Delayed interrupt generation module Low-power consumption mode
Initial value
9EH 9FH A0H A1H A2H to A4H A5H A6H A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH
0 0 0 0 0 0 0 0B
- - - - - - - 0B
0 0 0 1 1 0 0 -B 1 1 1 1 1 1 0 0B
(Disabled) Auto-ready function selection register External address output control register Bus control signal selection register Watch dog timer control register Time-base timer control register Clock timer control register ARSR HACR ECSR WDTC TBTC WTC (Disabled) Flash memory control status register FMCS R/W, R or W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller Flash interface 0 0 0 X 0 0 0 0B W W W R or W R/W, W R/W Watch dog timer Timebase timer Clock timer External bus pin control circuit 0 0 1 1 - - 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B XXXXX 1 1 1B 1 - - 0 0 1 0 0B 1 X 0 0 0 0 0 0B
(Disabled) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 31
MB90580B Series
(Continued) (Continued)
Address C0H to FFH 100H to #H #H to 1FEFH 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 1FF6H to 1FFFH Program address detection register 0 (lower) Program address detection register 1 (middle) Program address detection register 2 (upper) Program address detection register 3 (lower) Program address detection register 4 (middle) Program address detection register 5 (upper) PADR1 PADR0 Register name Abbreviated register Read/write name (External area) (RAM area) (Reserved area) R/W R/W R/W R/W R/W R/W (Reserved area) Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Resource name Initial value
* Explanation of initial values"0" : initial value"0" / "1" : initial value"1" / "X" : undefined / "-" : undefined (not used) * The addresses following 00FFH are reserved. No external bus access signal is generated. * Boundary #H between the RAM area and the reserved area varies with the product model. Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed.
32
MB90580B Series
s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt source Reset INT9 instruction Exception A/D converter Timebase timer DTP0 (external interrupt #0) /UART3 reception complete DTP1 (external interrupt #1) /UART4 reception complete DTP2 (external interrupt #2) /UART3 transmission complete DTP3 (external interrupt #3) /UART4 transmission complete DTP4 to 7 (external interrupt #4 to #7) Output compare (ch.1) match (I/O timer) UART2 reception complete UART1 reception complete Input capture (ch.3) include (I/O timer) Input capture (ch.2) include (I/O timer) Input capture (ch.1) include (I/O timer) Input capture (ch.0) include (I/O timer) 8/16 bit PPG0 counter borrow 16 bit reload timer 2 to 0 Clock prescaler Output compare (ch.0) match (I/O timer)
UART2 transmission complete
EI2OS support x x x x
Interrupt vector No. #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H
Interrupt control register ICR ICR00 Address 0000B0H
Priority High
ICR01 FFFFC4H FFFFC0H ICR02 FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF68H FFFF60H FFFF58H FFFF54H ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000B1H
0000B2H
0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Low
x x
#25 #26 #27 #28 #29 #30 #31 #32 #33
PWC timer measurement complete / over flow
UART1 transmission complete
16-bit free run timer (I/O timer) over flow
UART0 transmission complete
8/16 bit PPG1 counter borrow IEBus reception complete IEBus transmission start UART0 reception complete Flash memory status Delayed interrupt
x
#34 #35 #37 #39
x x
#41 #42
: Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal (stop request present). : Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal. x : Indicates that the interrupt request flag is not cleared by the EI2OS interrupt clear signal. 33
MB90580B Series
s PERIPHERAL RESOURCES
1. I/O Ports When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. Note that, if a read modify write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. Ports 0 to 4 and 6 to A are input/output ports which serve as inputs when the direction register value is "0" or as outputs when the value is "1". On the MB90580B series, ports 0 to 3 also serve as external bus pins. When the device is used in external bus mode, therefore, these ports are restricted on use. Ports 2 and 3 can be used as ports even in external bus mode depending on the setting of the corresponding function select bit. (2) Register configuration
* Port 0 data register (PDR0)
(1) Outline of I/O ports
bit 15 ............ 8
(PDR1)
7 P07
6 P06
5 P05
4 P04
3 P03
2 P02
1 P01
0 P00
Address
: 000000H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Port 1 data register (PDR1)
bit Address : 000001H
15 P17
14 P16
13 P15
12 P14
11 P13
10 P12
9 P11
8 P10
7 ............ 0 (PDR0)
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X)
* Port 2 data register (PDR2)
bit 15 ............ 8
(PDR3)
7 P27
6 P26
5 P25
4 P24
3 P23
2 P22
1 P21
0 P20
Address
: 000002H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Port 3 data register (PDR3)
bit Address : 000003H Access Initial value
* Port 4 data register (PDR4)
15 P37
14 P36
13 P35
12 P34
11 P33
10 P32
9 P31
8 P30
7 ............ 0 (PDR2)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
bit 15 ............ 8
(PDR5)
7 P47
6 P46
5 P45
4 P44
3 P43
2 P42
1 P41
0 P40
Address
: 000004H Access Initial value
(R/W) (RW) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
(Continued)
34
MB90580B Series
(Continued)
* Port 5 data register (PDR5) 7 ............ 0 (PDR4)
bit Address : 000005H Access Initial value
* Port 6 data register (PDR6)
15 P57
14 P56
13 P55
12 P54
11 P53
10 P52
9 P51
8 P50
(R/8) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1)
bit 15 ............ 8
(PDR7)
7 P67
6 P66
5 P65
4 P64
3 P63
2 P62
1 P61
0 P60
Address
: 000006H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Port 7 data register (PDR7)
bit Address : 000007H Access Initial value
* Port 8 data register (PDR8)
15 () ()
14 () ()
13
12 P74
11 P73
10 P72
9 P71
8
7 ............ 0 (PDR6)
() (R/W) (R/W) (R/W) (R/W) () () (X) (X) (X) (X) ()
bit 15 ............ 8
(PDR9)
7 P87
6 P86
5 P85
4 P84
3 P83
2 P82
1 P81
0 P80
Address
: 000008H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Port 9 data register (PDR9)
bit Address : 000009H Access Initial value
* Port A data register (PDRA)
15 P97
14 P96
13 P95
12 P94
11 P93
10 P92
9 P91
8 P90
7 ............ 0 (PDR8)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
bit 15 ............ 8 (Disabled)
7 () ()
6 () ()
5 () ()
4 () ()
3 () ()
2 PA2
1 PA1
0 PA0
Address
: 00000AH Access Initial value
(R/W) (R/W) (R/W) (X) (X) (X)
* Port 0 direction register (DDR0)
bit 15 ............ 8
(DDR1)
7 D07
6 D06
5 D05
4 D04
3 D03
2 D02
1 D01
0 D00
Address
: 000010H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
(Continued)
35
MB90580B Series
(Continued)
* Port 1 direction register (DDR1) 7 ............ 0 (DDR0)
bit Address : 000011H Access Initial value
* Port 2 direction register (DDR2)
15 D17
14 D16
13 D15
12 D14
11 D13
10 D12
9 D11
8 D10
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit 15 ............ 8
(DDR3)
7 D27
6 D26
5 D25
4 D24
3 D23
2 D22
1 D21
0 D20
Address
: 000012H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 3 direction register (DDR3)
bit Address : 000013H Access Initial value
* Port 4 direction register (DDR4)
15 D37
14 P36
13 P35
12 P34
11 P33
10 P32
9 P31
8 P30
7 ............ 0 (DDR2)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit 15 ............ 8
(DDR5)
7 D47
6 D46
5 D45
4 D44
3 D43
2 D42
1 D41
0 D40
Address
: 000014H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 5 direction register (DDR5)
bit Address : 000015H Access Initial value
* Port 6 direction register (DDR6)
15 D57
14 D56
13 D55
12 D54
11 D53
10 D52
9 D51
8 D50
7 ............ 0 (DDR4)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit 15 ............ 8
(DDR7)
7 D67
6 D66
5 D65
4 D64
3 D63
2 D62
1 D61
0 D60
Address
: 000016H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 7 direction register (DDR7)
bit Address : 000017H Access Initial value
15 () ()
14 () ()
13
12 D74
11 D73
10 D72
9 D71
8
7 ............ 0 (DDR6)
() (R/W) (R/W) (R/W) (R/W) () () (0) (0) (0) (0) ()
(Continued)
36
MB90580B Series
* Port 8 direction register (DDR8)
bit 15 ............ 8
(DDR9)
7 D87
6 D86
5 D85
4 D84
3 D83
2 D82
1 D81
0 D80
Address
: 000018H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 9 direction register (DDR9)
............ 8 14 bit 15 15
13 7
12 6
11 5
10 4
9 3
8 2
............ 0 71 0
Address
: 000019H Access Initial value
D97 D96 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 D95 D94 D93 D92 D91 D90 (DDR8) (RDR1) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
* Port A direction register (DDRA)
bit 15 ............ 8
(ODR4)
7 () ()
6 () ()
5 () ()
4 () ()
3 () ()
2 DA2
1 DA1
0 DA0
Address
: 00001AH Access Initial value
(R/W) (R/W) (R/W) (0) (0) (0)
* Port 4 output pin register (ODR4)
bit Address : 00001BH Access Initial value
15
14
13
12
11
10
9
8
7 ............ 0 (DDRA)
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 5 analog input enable register (ADER) bit 15 ............ 8
7
6
5
4
3
2
1
0
Address
: 00001CH Access Initial value
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1)
* Port 0 input pull-up resistor setup register (RDR0) bit 15 ............ 8 7
6
5
4
3
2
1
0
Address
: 00008CH Access Initial value
(RDR1)
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 1 input pull-up resistor setup register (RDR1) bit 15 14 13
12
11
10
9
8
7 ............ 0 (RDR0)
Address
: 00008DH Access Initial value
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* Port 6 input pull-up resistor setup register (RDR6) bit 15 ............ 8 7
6
5
4
3
2
1
0
Address
: 00008EH Access Initial value
(CDCR4)
RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
37
MB90580B Series
(3) Block Diagram
* Input/output port
Internal data bus
Data register read Data register Data register write Direction register Direction register write Pin
Direction register read
* Input pull-up resistor setup register
Pull-up resistor (About 50 k)
Data register
Port I/O
Direction register
Input pull-up resistor setup register
Bus
38
MB90580B Series
* Output pin register
Data register
Port I/O
Direction register
Pin register
Bus
39
MB90580B Series
2. Timebase Timer
The time-base timer consists of a 18-bit timer and an interval interrupt control circuit. Note that the time-base timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR. (1) Register configuration
* Timebase timer control register
bit Address : 0000A9H Access Initial value (2) Block Diagram
TBTC TBC1 TBC0 TBR TBIE TBOF AND Q
15
Reserved
14 () ()
13 () ()
12
11
10 (W) (1)
9
8 TBTC
TBIE TBOF TBR (R/W) (R/W) (0) (0)
TBC1 TBC0 (R/W) (R/W) (0) (0)
(R/W) (1)
Main clock Selector
212 214 216 219 TBTRES
Clock input Time-base timer
211 213 215 218
S R
Time-base interrupt
WDTC WT2 WT1 WT0 WTE WTC
Selector
2-bit counter
CLR
OF
Watchdog reset generator
CLR
To WDGRST internal reset generator
F2MC-16LX bus
WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF
AND S R
Q
Selector
210 213 214 215 WTRES
210 213 214 215
Clock timer Clock input Subclock
AND
Q
S R
Clock interrupt
WDTC PONR STBR WRST ERST SRST
From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register
40
MB90580B Series
3. Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit time-base timer as the clock source, a control register, and a watchdog reset control section. (1) Register configuration
* Watchdog timer control register
bit Address : 0000A8H Access Initial value (2) Block Diagram
7 (R) (X)
6 (R) (X)
5 (R) (X)
4 (R) (X)
3 (R) (X)
2 (W) (1)
1 (W) (1)
0 WDTC (W) (1)
PONR STBR WRST ERST SRST WTE WT1 WT0
Main clock
TBTC TBC1 TBC0 TBR TBIE TBOF AND Q S R
Selector
212 214 216 219 TBTRES
Clock input Time-base timer
211 213 215 218
Time-base interrupt
WDTC WT2 WT1 WT0 WTE WTC
Selector
2-bit counter
CLR
OF
Watchdog reset generator
CLR
To WDGRST internal reset generator
F2MC-16LX bus
WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF
AND S R
Q
Selector
210 213 214 215 WTRES
210 213 214 215
Clock timer Clock input Subclock
AND
Q
S R
Clock interrupt
WDTC PONR STBR WRST ERST SRST
From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register 41
MB90580B Series
4. Clock timer
The clock timer has the functions of a watchdog timer clock source, a subclock oscillation settling time wait timer, and of a periodically interrupt generating interval timer. (1) Register configuration
* Clock timer control register
bit Address : 0000AAH Access Initial value (2) Block Diagram
7 (R/W) (1)
6 (R) (X)
5
4
3
2
1
0 WTC
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0)
Main clock
TBTC TBC1 TBC0 TBR TBIE TBOF AND Q S R
Selector
212 214 216 219 TBTRES
Clock input Time-base timer
211 213 215 218
Time-base interrupt
WDTC WT2 WT1 WT0 WTE WTC
Selector
2-bit counter
CLR
OF
Watchdog reset generator
CLR
To WDGRST internal reset generator
F2MC-16LX bus
WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF
AND S R
Q
Selector
210 213 214 215 WTRES
210 213 214 215
Clock timer Clock input Subclock
AND
Q
S R
Clock interrupt
WDTC PONR STBR WRST ERST SRST
From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register
42
MB90580B Series
5. External Memory Access (External Bus Pin Control Circuit)
The external bus pin control circuit controls external bus pins used to expand the address/data buses of the CPU outside. (1) Register configuration
* Automatic ready function selection register 15 bit
14
13
12
11 () ()
10 () ()
9
8 ARSR
Address
: 0000A5H Access Initial value
IOR1 IOR0 HMR1 HMR0 (W) (0) (W) (0) (W) (1) (W) (1)
LMR1 LMR0 (W) (0) (W) (0)
* External address output control register
bit Address : 0000A6H Access Initial value
* Bus control signal selection register
7 E23 (W) (0)
6 E22 (W) (0)
5 E21 (W) (0)
4 E20 (W) (0)
3 E19 (W) (0)
2 E18 (W) (0)
1 E17 (W) (0)
0 E16 (W) (0) HACR
bit Address : 0000A7H Access Initial value
(2) Block Diagram
15 CKE (W) (0)
14 RYE (W) (0)
13
12
11
10
9
8 () () ECSR
HDE IOBS HMBS WRE LMBS (W) (0) (W) (0) (W) (0) (W) (0) (W) (0)
P0
P0 data P0 direction
P1
P2
P3 P3 P0
RB
Data control Address control Access control Access control
43
MB90580B Series
6. PWC Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-counter with reload timer functions and inputsignal pulse-width count functions as well. The PWC timer consists of a 16-bit counter, a input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. (1) Features of the PWC timer The PWC timer has the following features: * Timer functions Generates an interrupt request at set time intervals. Outputs pulse signals synchronized with the timer cycle. Selects the counter clock from among three internal clocks. * Pulse-width count functions Counts the time between external pulse input events. Selects the counter clock from among three internal clocks. Count mode *H pulse width (rising edge to falling edge)/L pulse width (falling edge to rising edge) *Rising-edge cycle (rising edge to falling edge)/Falling-edge cycle (falling edge to rising edge) *Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation.
44
MB90580B Series
(2) Register configuration
* PWC control status register (Upper byte)
bit Address : 000055H Access Initial value
15
14
13
12 EDIE
11 OVIR
10 OVIE
9
8
STRT STOP EDIR
ERR POUT PWCSR upper
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* PWC control status register (Lower byte)
bit Address : 000054H Access Initial value
7
6
5
4
3 S/C
2
1
0
CKS1 CKS0
ReservedReserved
MOD2 MOD1 MOD0 PWCSR lower
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
* PWC data buffer register (Upper byte)
bit Address : 000057H Access Initial value
15
14
13
12
11
10
9
8
PWCR upper
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* PWC data buffer register (Lower byte)
bit Address : 000056H Access Initial value
* Divide ratio control register
7
6
5
4
3
2
1
0
PWCR lower
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
bit Address : 000058H Access Initial value
* PWC noise filter register
7 () ()
6 () ()
5 () ()
4 () ()
3 () ()
2 () ()
1 DIV1
0 DIV0 DIVR
(R/W) (R/W) (0) (0)
bit Address : 000086H Access Initial value
7 () ()
6 () ()
5 () ()
4 () ()
3 () ()
2 EN
1 SW1
0 SW0 RNCR
(R/W) (R/W) (R/W) (0) (0) (0)
45
MB90580B Series
(3) Block Diagram
PWCR read
16
Error detection
ERR PWCR
16
16
Write enable
Reload
Data transfer
Overflow
Internal clock (Machine clock/4)
16
Clock 16-bit up-count timer Timer clear Count enable
22 23 CKS1, CKS0
F2MC-16LX bus
Clock divider
Control circuit
Control bit output Start edge End edge selection selection Count end edge Edge detection Count start edge
Divider clear
Divider ON/OFF
PWC
Flag set
Count end interrupt request Overflow interrupt request
ERR
CKS1 CKS0
8-bit divider
Overflow Divide ratio selection
2 DIVR F.F. POT
15
PWCSR
46
MB90580B Series
7. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, four input capture circuits, and two output comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run timer. Input pulse width and external clock periods can, therefore, be measured. (1) 16-bit free-run timer (1 channel) The 16-bit free run timer consists of a 16-bit up-counter, a control register, and a prescaler. The value output from this timer/counter is used as the base time for the input capture and output compare modules. * Counter operation clock (Selectable from among the following four) Four internal clock cycles: /4, /16, /64, /256 : Machine clock * Interrupts An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or by compare/match operation with compare register 0. (The compare/match operation requires the mode setting). * Counter value An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or when a match with compare register 0 occurs (The compare/match function can be used by the appropriate mode setting). * Initialization The counter value can be initialized to "0000H" at a reset, soft clear operation, or a match with compare register 0. (2) Output compare module (2 channels) The output compare module consists of two 16-bit compare registers, compare output latches, and control registers. When the 16-bit free-run timer value matches the compare register value, this module generates an interrupt while inverting the output level. * Two compare registers can operate independently. Output pin and interrupt flag for each compare register * A pair of compare registers can be used to control the output pin. Two compare registers can be used to invert the output pin polarity. * The initial value for each output pin can be set. * An interrupt can be generated by compare/match operation. (3) Input capture module (4 channels) The input capture module consists of capture registers and control registers respectively associated with four independent external input pins. This module can hold the 16-bit free run timer value in the capture register. In addition, it can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt. * The external input signal edge to be detected can be selected. One or both of the rising and falling edges can be selected. * Four input capture channels can operate independently. * An interrupt can be generated at a valid edge of the external input signal. The extended intelligent I/O service can be activated by the interrupt by the input capture module.
47
MB90580B Series
(4) Register configuration
* Timer data register (upper)
bit Address : 00006DH Access Initial value
* Timer data register (lower)
15 T15
14 T14
13 T13
12 T12
11 T11
10 T10
9 T09
8 T08 TCDTH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 00006CH Access Initial value
* Timer control status register
7 T07
6 T06
5 T05
4 T04
3 T03
2 T02
1 T01
0 T00 TCDTL
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 00006EH Access Initial value
* Compare register (upper)
7
Reserved
6
5
4
3
2
1
0 TCCS
IVF IVFE STOP MODE CLR CLK1 CLK0
() (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : ch0 00005BH : ch1 00005DH Access Initial value
15 C15
14 C14
13
12
11
10 C09
9 C08
8 OCCP0 OCCP1
C13 C12
C11
C10
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Compare register (lower)
bit Address : ch0 00005AH : ch1 00005CH Access Initial value
7 C07
6 C06
5 C05
4 C04
3 C03
2
1
0 C00 OCCP0 OCCP1
C02 C01
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Compare control status register 1
bit Address : ch1 00005FH Access Initial value
* Compare control status register 0
15 () ()
14 () ()
13 () ()
12
11
10
9
8 OCS1
CMOD OTE1 OTE0 OTD1 OTD0 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0)
bit Address : ch0 00005EH Access Initial value
7
6
5
4
3 () ()
2
1
0 OCS0
ICP1 ICP0 ICE1 ICE0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0)
CST1 CST0
() (R/W) (R/W) () (0) (0)
(Continued)
48
MB90580B Series
(Continued)
* Input capture register (upper)
Address
bit : ch0 000061H : ch1 000063H : ch2 000065H : ch3 000067H Access Initial value
15
14
13
12
11
10
9
8 IPCP0 upper IPCP1 upper IPCP2 upper IPCP3 upper
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X)
* Input capture register (lower)
Address
bit : ch0 000060H : ch1 000062H : ch2 000064H : ch3 000066H Access Initial value
7
6
5
4
3
2
1
0 IPCP0 lower IPCP1 lower IPCP2 lower IPCP3 lower
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X)
* Control status register 01
bit Address : 000068H Access Initial value
* Control status register 23
7
6
5
4
3
2
1
0 ICS01
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 00006AH Access Initial value
7
6
5
4
3
2
1
0 ICS23
ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
49
MB90580B Series
(5) Block Diagram
Interrupt request
IVF IVFE STOP MODE CLR CLK1 CLK0
Frequency divider
Comparator 0 16-bit up-counter Output count value (T15 to T00) Compare control Compare register ch.0
CMOD OUT0
Clock
F2MC-16LX bus
T
Q
OTE0
Compare control Compare register ch.1
ICP1 ICP0 ICE1
T
Q
OTE1
OUT1
ICE0
Compare interrupt 0 Control block
Each control block Input capture data register ch.0, ch.2 Edge detection
IN0, IN2
Compare interrupt 1
EG11 EG10 EG01 EG00
Input capture data register ch.1, ch.3
Edge detection
ICP0 ICE1 ICE0
IN1, IN3
ICP1
Capture interrupt 1/3 Capture interrupt 0/2
50
MB90580B Series
8. 16-bit Reload Timer
The 16-bit reload timer has three channels, each of which consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from among three internal clocks and one external clock. (1) Register configuration
* Timer control status register (upper)
Address
bit : ch0 000049H : ch1 00004DH : ch2 000051H Access Initial value
15 () ()
14
13
12
11
10
9
8 TMCSR0 upper TMCSR1 upper TMCSR2 upper
CSL1 CSL0 MOD2 MOD1
() ()
() ()
() (R/W) (R/W) (R/W) (R/W) () (0) (0) (0) (0)
* Timer control status register (lower)
Address
bit : ch0 000048H : ch1 00004CH : ch2 000050H Access Initial value
7
6
5
4
3
2
1
0 TMCSR0 lower TMCSR1 lower TMCSR2 lower
MOD0 OUTE OUTL RELD INTE
UF CNTE TRG
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (read) TMR0 upper TMR1 upper TMR2 upper (write) TMRLR0 upper TMRLR1 upper TMRLR2 upper (read) TMR0 lower TMR1 lower TMR2 lower (write) TMRLR0 lower TMRLR1 lower TMRLR2 lower
* 16-bit timer register (upper) /16 bit reload register (upper)
Address
bit : ch0 00004BH : ch1 00004FH : ch2 000053H Access Initial value
15
14
13
12
11
10
9
8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* 16-bit timer register (lower) /16 bit reload register (lower)
Address
bit : ch0 00004AH : ch1 00004EH : ch2 000052H Access Initial value
7
6
5
4
3
2
1
0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
51
MB90580B Series
(2) Block Diagram
16
16-bit reload register
8
Reload
RELD
16-bit down-counter UF
16 2
OUTE OUTL
F2MC-16LX bus
GATE CSL1
OUT CTL.
INTE UF IRQ
Clock selector
CSL0
CNTE
Retrigger
2 IN EXCK ------ 21 23 25 CTL 3 MOD2 MOD1
TRG
Clear EI2OSCLR Port (TIN) Port (TOT)
Output enable
Prescaler clear
Machine clock
3
Serial baud rate (channel n)
MOD0
Note: Reload timer channels and UART channels are connected as follows *Reload timer channel 0 : UART0, UART3 *Reload timer channel 1 : UART1, UART4 *Reload timer channel 2 : UART2
52
MB90580B Series
9. 8/16-bit PPG
8/16-bit PPG is an 8/16-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. * 8-bit PPG output in two channels independent operation mode: Two independent PPG output channels are available. * 16-bit PPG output operation mode : One 16-bit PPG output channel is available. * 8 + 8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. * PPG output operation : Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register configuration
* PPG0 operating mode control register
bit Address : ch0 0000044H Access Initial value
* PPG1 operating mode control register
7 PEN0
6
5
4
3
2
1
0
Reserved
POE0 PIE0 PUF0
PPGC0
(R/W) () (R/W) (R/W) (R/W) () (0) () (0) (0) (0) (X)
() (R/W) (X) (1)
bit Address : ch1 0000045H Access Initial value
* PPG0 and 1 output control registers
15 PEN1
14
13
12
11
10
9
8
Reserved
POE1 PIE1 PUF1 MD1 MD0
PPGC1
(R/W) () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) () (0) (0) (0) (0) (0) (1)
bit Address : ch0, 1 0000046H Access Initial value
* Reload register H
7
6
5
4
3
2
1
0 PPGOE
PCS2 PCS1 PCS0 PCM2PCM1PCM0
ReReserved served
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : ch0 000041H : ch1 000043H Access Initial value
15
14
13
12
11
10
9
8 PRLH0 PRLH1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Reload register L
bit Address : ch0 000040H : ch1 000042H Access Initial value
7
6
5
4
3
2
1
0 PRLL0 PRLL1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 53
MB90580B Series
(2) Block Diagram
* Block diagram (8 bit PPG (ch.0) )
PPG0 output enable
Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock
PPG0
PPG0 output latch Invert Clear
PEN0
PCNT (Down-counter)
Count clock selection
S RQ
IRQ
Reload
Timebase counter output oscillation clock divided by 512
ch.1 borrow L/H Selector
L/H select
PRLL0
PRLBH0 PIE0
PRLH0
PUF0
L-side data bus H-side data bus
PPGC0
(Operation mode control)
54
MB90580B Series
* Block Diagram (8/16 bit PPG (ch.1) )
PPG1 output enable
Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock
PPG1
A/D converter PPG1 output latch Invert Clear
PEN1
Count clock selection
ch0 borrow Timebase counter output oscillation clock divided by 512 L/H select
PCNT (Down-counter) Reload
S RQ
IRQ
L/H Selector
PRLL1
PRLBH1 PIE
PRLH1
PUF
L-side data bus H-side data bus
PPGC1
(Operation mode control)
55
MB90580B Series
10. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request levels ("H" and "L") are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on "H" and "L" levels can be selected, giving a total of four types. (1) Register configuration
* Interrupt/DTP enable register
bit Address : 0000030H Access Initial value
* Interrupt/DTP source register
7
6
5
4
3
2
1
0 ENIR
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 0000031H Access Initial value
* Request level setting register (lower)
15
14
13
12
11
10
9
8 EIRR
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
bit Address : 0000032H Access Initial value
* Request level setting register (upper)
7 LB3
6 LA3
5 LB2
4 LA2
3 LB1
2 LA1
1 LB0
0 LA0 ELVR lower
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 0000033H Access Initial value
15 LB7
14 LA7
13 LB6
12 LA6
11 LB5
10 LA5
9 LB4
8 LA4 ELVR upper
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
(2) Block Diagram F2MC-16LX bus
8
Interrupt/DTP enable register Gate
Source F/F Edge detect circuit
8
8
Request input
8
Interrupt/DTP source register
8
Request level setting register
56
MB90580B Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration The DIRR register controls generation and clearing of delayed interrupt requests. Writing "1" to the register generates a delayed interrupt request. Writing "0" to the register clears the delayed interrupt request. The register is set to the interrupt cleared state by a reset. Either "0" or "1" can be written to the reserved bits. However, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access.
* Delayed interrupt generation/release register
bit Address : 00009FH Access Initial value
15 () ()
14 () ()
13 () ()
12 () ()
11 () ()
10 () ()
9
8 R0 DIRR
() (R/W) () (0)
(2) Block Diagram
F2MC-16LX bus
Delayed interrupt generation/ release decode
Interrupt latch
57
MB90580B Series
12. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features. * Conversion time: Minimum of 34.7 s per channel (for a 12 MHz machine clock) * Uses RC-type successive approximation conversion with a sample and hold circuit. * 8/10-bit resolution * Eight program-selectable analog input channels Single conversion mode: Selectively convert one channel. Scan conversion mode: Continuously convert multiple channels. Maximum of 8 program selectable channels. Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode:Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) * An A/D conversion completion interrupt request. An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate EI2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. * Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) Register configuration
* Control status register (upper)
bit Address : 000037H Access Initial value
* Control status register (lower)
15
14
13
12
11
10
9
8
Reserved
BUSY INT INTE PAUS STS1 STS0 STRT
ADCS2
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) () (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 000036H Access Initial value
* Data register (upper)
7
6
5
4
3
2
1
0 ADCS1
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
bit Address : 000039H Access Initial value
* Data register (lower)
15 (W) (0)
14 (W) (0)
13 (W) (0)
12 (W) (0)
11 (W) (1)
10 () ()
9 D9 (R) (X)
8 D8 (R) (X) ADCR2
SELB ST1 ST0 CT1 CT0
bit Address : 000038H Access Initial value
7 D7 (R) (X)
6 D6 (R) (X)
5 D5 (R) (X)
4 D4 (R) (X)
3 D3 (R) (X)
2 D2 (R) (X)
1 D1 (R) (X)
0 D0 (R) (X) ADCR1
58
MB90580B Series
(2) Block Diagram
AVCC AVRH,AVRL AVSS
D/A converter
MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Successive approximation register
Comparator Sample and hold circuit Decoder Data register
ADCR1, 2
F2 M C 1 6 L X b u s
Control status register upper Control status register lower Trigger activation ADTG Timer activation PPG1 output
ADCS1, 2
Operating clock Prescaler
59
MB90580B Series
13. D/A Converter
D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The D/A control register controls the output of the two D/A converters independently. (1) Register configuration
* D/A converter data register 1
bit Address : 00003BH
15
14
13
12
11
10
9
8 DAT1
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0)
* D/A converter data register 0
bit Address : 00003AH
7
6
5
4
3
2
1
0 DAT0
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0)
* D/A control register 1
bit Address : 00003DH Access Initial value
* D/A control register 0
15 () ()
14 () ()
13 () ()
12 () ()
11 () ()
10 () ()
9
8 DAE1 DACR1
() (R/W) () (0)
bit Address : 00003CH Access Initial value
7 () ()
6 () ()
5 () ()
4 () ()
3 () ()
2 () ()
1
0 DAE0 DACR0
() (R/W) () (0)
60
MB90580B Series
(2) Block Diagram
F2MC16LX - BUS
DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00
DVR DA17 2R DA16 2R DA15 R DA07
DVR
2R DA06 2R DA05
R
R
R
DA11 2R DA10 R
DA01 2R DA00 R
2R 2R DAE1 DAE0
2R 2R
Standby control
Standby control
DA output channel 1
DA output channel 0
61
MB90580B Series
14. Communication Prescaler
The register (clock division control register) of the communication prescaler controls division of the machine clock frequency. It is designed to provide a fixed baud rate for a variety of machine clock frequencies depending on the user setting. The output from the communication prescaler is used by the UARTs. (1) Register configuration
* Clock division control registers 0 to 4
bit Address : 00002CH 00002EH Access 000034H Initial value 000087H 00008FH
15 MD
14
13 () ()
12
11
10
9
8 CDCR0 CDCR1 CDCR2 CDCR3 CDCR4
DIV3 DIV2 DIV1 DIV0
(R/W) () (0) ()
() (R/W) (R/W) (R/W) (R/W) () (1) (1) (1) (1)
62
MB90580B Series
15. UART
The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features: * Full-duplex double buffering * Capable of asynchronous (start-stop) and CLK-synchronous communications * Support for the multiprocessor mode * Dedicated baud rate generator integratedBaud rate Operation Asynchronous Baud rate 31250/9615/4808/2404/1202 bps
CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps * : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz * Capable of setting an arbitrary baud rate using an external clock * Error detection functions (parity, framing, overrun) * HRz sign transfer signal
(1) Register configuration
* Serial mode register
Address : 0000020H bit 0000024H 0000028H Access 0000082H Initial value 0000088H
* Serial control register
7
6
5
4
3
2
Reserved
1
0
MD1 MD0 CS2 CS1 CS0
SCKE SOE
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
SMR0 SMR1 SMR2 SMR3 SMR4
Address : 0000021H bit 0000025H 0000029H Access 0000083H Initial value 0000089H
15 PEN
14 P
13 SBL
12 CL
11
10
9
8
A/D REC RXE TXE
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) (0) (0)
SCR0 SCR1 SCR2 SCR3 SCR4
* Serial input register/serial output register
bit Address : 0000022H 0000026H Access 000002AH Initial value 0000084H 000008AH
* Serial status register
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
(read) (write) SIDR0 SODR0 SIDR1 SODR1 SIDR2 SODR2 SIDR3 SODR3 SIDR4 SODR4
Address : 0000023H bit 0000027H 000002BH Access 0000085H Initial value 000008BH
15 PE
14
13
12
11
10
9 RIE
8 TIE
ORE FRE RDRFTDRE
(R/W) (R/W) (R/W) (R/W) (R/W) () (R/W) (R/W) (0) (0) (0) (0) (1) () (0) (0)
SSR0 SSR1 SSR2 SSR3 SSR4
63
MB90580B Series
(2) Block Diagram Control signals Receive interrupt signal (to CPU) Dedicated baud rate generator 16 bit reload timer channel 0 to 2 External clock Clock select circuit Receive clock
SCK0 to SCK4
Transmit clock
Transmit interrupt signal (to CPU)
Receive control circuit Start bit detection circuit Receive bit counter Receive parity counter
Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter
SOT0 to SOT4
SIN0 SIN4
Receive condition decision circuit
Shift register for reception
Reception complete
Shift register for transmission
Start transmission
Reception error generation signal for EI2OS (to CPU)
SIDR0 to SIDR4
SODR0 to SODR4
F2MC-16LX bus
SMR0 to SMR4 register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR0 to SCR4 register
PEN P SBL CL A/D REC RXE TXE
SSR0 to SSR4 register
PE ORE FRE RDRF TDRE RIE TIE
Control signal
64
MB90580B Series
16. IEBusTM Controller
The IEBusTM (Inter-Equipment Bus) is a small-scale, two-wire serial bus interface designed for data transfer between pieces of equipment. This interface is applicable, for example, as a bus interface for controlling vehicle-mounted devices. IEBusTM has the following features: * Multitasking Any of the units connected to the IEBusTM can transmit data to another one. * Broadcast function (Communication from one unit to multiple units) Group broadcast : Broadcast to a group of units All-unit broadcast : Broadcast to all units * Three modes can be selected for different transmission speeds. IEBusTM internal frequency 6 MHz Mode 0 Mode 1 Mode 2 About 3.9 Kbps About 17 Kbps About 26 Kbps 6.29 MHz About 4.1 Kbps About 18 Kbps About 27 Kbps
* Data buffer for transmission 8-byte FIFO buffer * Data buffer for reception 8-byte FIFO buffer * CPU internal operating frequency (12 MHz, 12.58 MHz) * Frequency tolerance In mode 0 or 1 : 1.5% In mode 2 : 0.5% (1) Register configuration
* Local-office address setting register H
bit Address : 000071H Access Initial value
15
14
13
12
11
10
9
8 MAWH
Reserved Reserved Reserved Reserved
MA11 MA10 MA09 MA08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Local-office address setting register L
bit Address : 000070H Access Initial value
* Slave address setting register H
7
6
5
4
3
2
1
0 MAWL
MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
bit Address : 000073H Access Initial value
15
14
13
12
11
10
9
8 SAWH
Reserved Reserved Reserved Reserved
SA11 SA10 SA09 SA08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
(Continued)
65
MB90580B Series
* Slave address setting register L
bit Address : 000072H
7
6
5
4
3
2
1
0 SAWL
SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X)
* Broadcast control bit setting register
bit Address : 000075H
15
14
13
12
11 C3
10 C2
9 C1
8 C0 DCWR
DO3 DO2 DO1 DO0
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0)
* Broadcast control bit read register
bit Address : 00007FH Access Initial value
* Message length bit setting register
15 (R) (0)
14 (R) (0)
13 (R) (0)
12 (R) (X)
11 C3 (R) (X)
10 C2 (R) (X)
9 C1 (R) (X)
8 C0 (R) (X) DCRR
DO3 DO2 DO1 DO0
bit Address : 000074H
7 DE7
6 DE6
5 DE5
4 DE4
3 DE3
2 DE2
1 DE1
0 DE0 DEWR
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0)
* Message length bit read register
bit Address : 00007EH Access Initial value
* Command register H
7 DE7 (R) (X)
6 DE6 (R) (X)
5 DE5 (R) (X)
4 DE4 (R) (X)
3 DE3 (R) (X)
2 DE2 (R) (X)
1 DE1 (R) (X)
0 DE0 (R) (X) DERR
bit Address : 000077H
15
14
13
12
11
10
9
8 CMRH
MD1 MD0 PCOM RIE
TIE GOTMGOTS Reserved
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (X)
* Command register L
bit Address : 000076H
7 RXS
6 TXS
5
4
3 CS1
2
1
0 CMRL
TIT1 TIT0
CS0 RDBC WDBC
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (1) (0) (0) (0) (0) (0) (0)
* Status register H
bit Address : 000079H Access Initial value
15 COM
14 TE
13 PEF (R) (X)
12 ACK
11 RIF
10 TIF
9 TSL (R) (0)
8 EOD (R) (0) STRH
(R) (R/W) (0) (0)
(R) (R/W) (R/W) (X) (0) (0)
(Continued)
66
MB90580B Series
(Continued)
* Status register L
bit Address : 000078H
Access Initial value
7 (R) (0)
6 (R) (0)
5 (R) (1)
4 (R) (1)
3 ST3 (R) (X)
2 ST2 (R) (X)
1 ST1 (R) (X)
0 ST0 (R) (X) STRL
WDBF RDBF WDBE RDBE
* Lock read register H
bit Address : 00007BH Access Initial value
* Lock read register L
15 (R) (1)
14 (R) (1)
13 (R) (1)
12 LOC (R/W) (0)
11 (R) (X)
10 (R) (X)
9 (R) (X)
8 LRRH (R) (X)
Reserved Reserved Reserved
LD11 LD10 LD09 LD08
bit Address : 00007AH Access Initial value
* Master address read register H
7 LD07 (R) (X)
6 LD06 (R) (X)
5 LD05 (R) (X)
4 (R) (X)
3 (R) (X)
2 (R) (X)
1 (R) (X)
0 LRRL (R) (X)
LD04 LD03 LD02 LD01 LD00
bit Address : 00007DH Access Initial value
* Master address read register L
15 (R) (1)
14 (R) (1)
13 (R) (1)
12 (R) (1)
11 (R) (X)
10 (R) (X)
9 (R) (X)
8 MARH (R) (X)
Reserved Reserved Reserved Reserved
MA11 MA10 MA09 MA08
bit Address : 00007CH Access Initial value
* Read data buffer
7 (R) (X)
6 (R) (X)
5 (R) (X)
4 (R) (X)
3 (R) (X)
2 (R) (X)
1 (R) (X)
0 MARL (R) (X)
MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00
bit Address : 000081H Access Initial value
* Write data buffer
15 RD7 (R) (X)
14 RD6 (R) (X)
13 RD5 (R) (X)
12 RD4 (R) (X)
11 RD3 (R) (X)
10 RD2 (R) (X)
9 RD1 (R) (X)
8 RD0 (R) (X) RDB
bit Address : 000080H Access Initial value
7 WD7 (W) (X)
6 WD6 (W) (X)
5 WD5 (W) (X)
4 WD4 (W) (X)
3 (W) (X)
2 (W) (X)
1 (W) (X)
0 WDB (W) (X)
WD3 WD2 WD1 WD0
67
MB90580B Series
(2) Block Diagram
Local-office address setting register Slave address setting register F2MC-16LX internal bus Broadcast control bit setting register Message length bit setting register 8-byte FIFO, write data buffer Master address read register Broadcast control bit read register Message length bit read register Lock read register 8-byte FIFO, read data buffer Command register Status register Interrupt request signal (transmission/reception) Internal clock 12 MHz/12.58 MHz Control circuit IEBusTM protocol controller
TX
RX
2
Prescaler
6 MHz/6.29 MHz
IEBusTM controller The control circuit in the IEBusTM controller executes the following control functions: * Controls the number of bytes in data to be transmitted and received. * Controls the maximum number of bytes transmitted. * Detects the results of arbitration. * Evaluates the return of acknowledgment of each field. * Generates interrupt signals.
68
MB90580B Series
17. Clock Monitor Function
The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from the CKOT pin. (1) Register configuration
* Clock output enable register
bit Address : 00003EH Access Initial value
7 () ()
6 () ()
5 () ()
4
3
2
1
0 CLKR
CKEN FRQ2 FRQ1 FRQ0 () (R/W) (R/W) (R/W) (R/W) () (0) (0) (0) (0)
(2) Block Diagram
F2MC-16LX bus
CKEN FRQ2 FRQ1 FRQ0
Divider circuit
Machine clock
P65/CKOT
69
MB90580B Series
18. Address Match Detection Function
When an address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the CPU executes the INT9 instruction. The address match detection function is implemented by processing using the INT9 interrupt routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is "1", the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration
* Program address detection register 0 to 2 (PADR0) 7 bit
6
5
4
3
2
1
0
PADR0 (lower)
Address : 001FF0H Access Initial value bit
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 17 16 15 14 13 12 11 10
PADR0 (middle)
Address : 001FF1H Access Initial value bit
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0
PADR0 (upper)
Address : 001FF2H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Program address detection register 3 to 5 (PADR1) bit 17
16
15
14
13
12
11
10
PADR1 (lower)
Address : 001FF3H Access Initial value bit Address : 001FF4H Access Initial value bit
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0
PADR1 (middle)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 17 16 15 14 13 12 11 10
PADR1 (upper)
Address : 001FF5H Access Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
* Program address detection control/status register (PACSR) bit 7 6 5 4 3 2 1 0 ReReReReReReAD1E AD0E Address : 00009EH served served served served served served (-) (-) (-) (-) (R/W) (-) (R/W) (-) Access (0) (0) (0) (0) (0) (0) (0) (0) Initial value
70
MB90580B Series
(2) Block Diagram
Address detection register
Compare
Address latch
Enable bit
INT9 Instruction
F2MC-16LX CPU core
F2MC-16LX bus
71
MB90580B Series
19. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register configuration
* ROM mirroring function selection register
bit Address : 00006FH Access
15 ()
14 ()
13 ()
12 ()
11 ()
10 ()
9 ()
8 MI (W) ROMM
(2) Block Diagram F2MC-16LX bus
ROM mirroring function selection register Address area
Address
FF bank
00 bank
Data
ROM
72
MB90580B Series
20. One-Megabit Flash Memory
The 1Mbit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as "enable sector protect" cannot be used. Features of 1Mbit flash memory * 128K words x 8 bits or 64K words x 16 bits (16K + 512 x 2 + 7K + 8K + 32K + 64K) sector configuration * Automatic program algorithm (Embedded Algorithm*: Same as the MBM29F400TA) * Erasure suspend/resume function integrated * Detection of programming/erasure completion using the data polling or toggle bit * Detection of programming/erasure completion using CPU interrupts * Compatible with JEDEC standard commands * Capable of erasing data sector by sector (arbitrary combination of sectors) * Minimum number of times of programming/erasure: 100,000 * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration
* Flash memory control status register
bit Address : 0000AEH Access Initial value
7 INTE (R/W) (0)
6 RDYINT (R/W) (0)
5 WE (R/W) (0)
4 RDY (R) (X)
3
Reserved
2 LPM1 (R/W) (0)
1
Reserved
0 LPM0 (R/W) (0) FMCS
(W) (0)
(W) (0)
73
MB90580B Series
(2) Sector configuration of 1Mbit flash memory The 1Mbit flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When accessed from the CPU, SA0 and SA1 to SA4 are allocated in the FE and FF bank registers, respectively.
Flash memory SA4 (16 Kbytes)
CPU address FFFFFFH FFC000H FFBFFFH
Programmer address * 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H 6FFFFH 60000H
SA3 (8 Kbytes) FFA000H FF9FFFH SA2 (8 Kbytes) FF8000H FF7FFFH SA1 (32 Kbytes) FF0000H FEFFFFH SA0 (64 Kbytes) FE0000H
* : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel programmer. Programmer addresses are used to program/erase data using a general-purpose programmer.
74
MB90580B Series
21. Low-Power Consumption Control Circuit
The operation modes of the MB90580B series are the PLL clock, PLL sleep, watch, main clock, main sleep, stop, and hardware standby modes. The operation modes excluding the PLL clock mode are classified as lowpower consumption modes. The low power consumption circuit has the following functions. * Main clock mode/Main sleep mode In either mode, the microcontroller operates only with the main clock (OSC oscillation clock), using the main clock as the operating clock while suspending the PLL clock (VCO oscillation clock). * PLL sleep mode/Main sleep mode These modes stop only the operation clock of the CPU, leaving the other clocks active. * Watch mode The watch mode allows only the time-base timer to operate. * Stop mode/Hardware standby mode These modes stop oscillation while retaining data at the lowest power consumption. The CPU intermittent operation function causes the clock supplied to the CPU to operate intermittently when the CPU accesses a register, internal memory, internal resource, or external bus. This function saves power consumption by decreasing the execution speed of the CPU while providing high-speed clock signals to the internal resources. The PLL clock multiplication factor can be selected from among 1, 2, 3, and 4 using the CS1 and CS0 bits in the clock selection register. The WS1 and WS0 bits can be used to set the oscillation settling time for the main clock, which is taken to wake up from the stop or hardware standby mode. (1) Register configuration
* Low-power consumption mode control register
bit Address : 0000A0H Access Initial value
* Clock selection register
7 (W) (0)
6
5
4
3
2
1
0 LPMCR
STP SLP SPL RST TMD CG1 CG0 (W) (R/W) (W) (0) (0) (1)
() (R/W) (R/W) () (1) (0) (0) ()
bit Address : 0000A1H Access Initial value
15 (R) (1)
14
13
12
11
10
9
8 CKSCR
SCM MCM WS1 WS0 SCS MCS CS1 CS0 (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (0) (0)
75
MB90580B Series
(2) Block Diagram
CKSCR SCM SCS CKSCR MCM MCS CKSCR
Subclock switching controller
Sub clock (OSC oscillation)
PLL multiplication circuit
1 2 3 4
Main clock (OSC oscillation) CPU clock generation
1/2 S
F2MC-16LX bus
CPU clock
CS1 CS0 LPMCR CG1 CG0
CPU clock selector
0/9/17/33 intermittent cycle selection
CPU intermittent operation cycle selector Peripheral clock generation
SLEEP
Peripheral clock
LPMCR SLP STP TMD
SCM
Standby control circuit
RST
MSTP STOP
Main OSC stop Sub OSC stop
Cancel
HST Start HST pin Interrupt request or RST
CKSCR WS1 WS0 LPMCR SPL
Oscillation stability waiting time selector
210 213 215 218
Clock input Timebase timer
212 214 216 219
Pin hi-impedance control circuit
Internal reset generation signal circuit
Pin Hi-Z
LPMCR RST
RST pin Internal RST To watchdog timer
WDGRST
76
MB90580B Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 15 4 100 50 -15 -4 -100 -50 300 +85 +150 (VSS = AVSS = 0.0 V) Unit V V V V V V mA mA mA mA mA mA mA mA mW C C Average output current = operating current x operating efficiency Average output current = operating current x operating efficiency *3 Average output current = operating current x operating efficiency VCC AVCC *1 AVCC AVRH/L, AVRH AVRL VCC DVCC *2 *2 *3 Average output current = operating current x operating efficiency Remarks
Parameter
Symbol VCC
Power supply voltage
AVCC AVRH, AVRL DVCC VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
*1 : AVCC shall never exceed VCC when power on. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
77
MB90580B Series
2. Recommended Operating Conditions
Value Min. 3.0 4.5 VCC VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage VILS VILM 3.0 0.7 VCC 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. 5.5 5.5 5.5 VCC+0.3 VCC+0.3 VCC+0.3 0.3 VCC 0.2 VCC VSS+0.3
(VSS = AVSS = 0.0 V) Unit V V V V V V V V V Remarks Normal operation (MB90583B, MB90587, MB90V580) Normal operation (MB90F583B) Retains status at the time of operation stop CMOS input pin CMOS hysteresis input pin MD pin input CMOS input pin CMOS hysteresis input pin MD pin input Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS.
Parameter
Symbol
Power supply voltage
VCC
Smoothing capacitor
CS
0.1
1.0
F
Operating temperature
TA
-40
+85
C
* C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 78
MB90580B Series
3. DC Characteristics
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Condition VCC = 4.5 V, IOH = -2.0 mA VCC = 4.5 V, IOL = 2.0 mA VCC = 5.5 V, VSS < VI< VCC VCC = 5.0 V, Internal operation at 16 MHz, Normal operation VCC = 5.0 V, Internal operation at 12.58 MHz, Normal operation Value Min. VCC - 0.5 -5 Typ. 27 40 22 35 Max. 0.4 5 33 50 26 45 Unit V V A mA MB90583B, MB90587 Remarks
Parameter "H" level output voltage "L" level output voltage Input leakage current
Symbol Pin name VOH VOL IIL All output pins All output pins All input pins
mA MB90F583B mA MB90583B mA MB90F583B
ICC
VCC = 5.0 V, Internal operation at 16 MHz, When data written in flash mode programming of erasing VCC = 5.0 V, Internal operation at 12.58 MHz, When data written in flash mode programming of erasing VCC = 5.0 V, Internal operation at 16 MHz, , In sleep mode VCC = 5.0 V Internal operation at 12.58 MHz, In sleep mode VCC = 5.0 V, Internal operation at 8 kHz, Subsystem operatin, TA = 25 C
45
60
mA
MB90F583B
Power supply current*
VCC
40
50
mA

7 15 6 12 0.1 4
12 20 10 18 1.0 7
mA MB90587 mA MB90583B, MB90F583B
ICCS
mA MB90587 mA mA MB90583B, MB90F583B MB90583B, MB90587
ICCL
mA MB90F583B
(Continued)
79
MB90580B Series
(Continued)
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition VCC = 5.0 V, Internal operation at 8 kHz, In subsleep mode, TA = 25 C VCC ICCT VCC = 5.0 V, Internal operation at 8 kHz, In clock mode, TA = 25 C In stop mode, TA = 25 C Except AVCC, AVSS, C, VCC and VSS P40 to P47 P00 to P07 P10 to P17 P60 to P65 RST MD2 Value Min. Typ. Max. Unit Remarks
Parameter
ICCLS
30
50
A
MB90583B, MB90587, MB90F583
Power supply current*
15
30
A
MB90583B, MB90587, MB90F583B MB90583B MB90587, MB90F583B
ICCH
5
20
A
Input capacitance Open-drain output leakage current Pull-up resistance Pull-down resistance *
CIN
10
80
pF
Ileak
0.1
5
A
Open-drain output setting
RUP
25
50
100
k
RDOWN
25
50
100
k
The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock.
80
MB90580B Series
4. AC Characteristics
(1) Clock Timings (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) ConSymbol Pin name dition fC fCL tHCYL tLCYL f PWH PWL PWLH PWLL tCR tCF fCP fLCP tCP tLCP X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min. 3 62.5 10 1.5 62.5 Typ. 32.768 30.5 15.2 8.192 -- 122.1 Max. 16 333 5 5 16 666 Unit MHz kHz ns s % ns s ns Remarks
Parameter Clock frequency Clock cycle time Frequency fluctuation rate locked*
Input clock pulse width
Recommened duty ratio of 30% to 70% External clock operation
Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time
MHz Main clock operation kHz Subclock operation ns s Main clock operation Subclock operation
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked.
+ fo + x 100 (%)
f =
Center frequency
fo - -
* X0, X1 clock timing X0
PWH
tHCYL 0.8 VCC 0.2 VCC PWL tCF tCR
* X0A, X1A clock timing
tLCYL 0.8 VCC 0.2 VCC PWLH tCF PWLL tCR
X0A
81
MB90580B Series
* PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V) Operation guarantee range of MB90F583B
5.5
4.5
3.3 3.0
Operation guarantee range of MB90583B/7, MB90V580B
1 3 8 12
Operation guarantee range of PLL
16
Internal clock fCP (MHz) Relationship between oscillating frequency and internal operating clock frequency
Multiplied- Multiplied- Multipliedby-3 by-4 by-2 Multipliedby-1
16
Internal clock fCP (MHz)
12 9 8
Not multiplied
4
3
4
8
16
Oscillation clock fCP (MHz)
The AC ratings are measured for the following measurement reference voltages
* Input signal waveform * Output signal waveform
Hystheresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Pins other than hystheresis input/MD input
0.7 VCC 0.3 VCC
82
MB90580B Series
(2) Clock Output Timings
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tCYC tCHCL Pin name CLK Condition VCC = 5 V 10% Value Min. 62.5 20 Max. Unit ns ns Remarks
Parameter Clock cycle time CLK CLK
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
(3) Reset, Hardware Standby Input Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Condition Value Min. 4 tCP 4 tCP Max. Unit ns ns Remarks
Parameter Reset input time Hardware standby input time
Symbol tRSTL tHSTL
Pin name RST HST
tRSTL, tHSTL
RST HST
0.2 VCC
0.2 VCC
83
MB90580B Series
(4) Power-on Reset
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition tR tOFF VCC VCC Value Min. 0.05 4 Max. 30 Unit ms ms Due to repeated operations Remarks
Parameter Power supply rising time Power supply cut-off time
Note : - VCC must be kept lower than 0.2 V before power-on. - The above values are used for causing a power-on reset. - If HST = "L", be sure to turn the power supply on using the above values to cause a power-on reset whether or not the power-on reset is required. - Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock.
VCC 3.0 V VSS
RAM data hold
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
84
MB90580B Series
(5) Bus Timing (Read)
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 A23 to A16, AD15 to AD00, RD A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 RD, ALE ALE, A23 to A16 A23 to A16, AD15 to AD00, CLK RD, CLK ALE, RD Condition Value Min. tCP/2 - 20 tCP/2 - 20 tCP/2 - 15 tCP - 15 3 tCP/2 - 20 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 20 tCP/2 - 20 tCP/2 - 15 Max. 5 tCP/2 - 60 3 tCP/2 - 60 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter ALE pulse width Effective address ALE time ALE address effective time Effective address RD time Effective address valid data input RD pulse width RD valid data input RD data hold time RD ALE time RD address effective time Effective address CLK time RD CLK time ALE RD time
Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL
85
MB90580B Series
* Bus Timing (Read)
tAVCH 2.4 V tRLCH 2.4 V
CLK
tRHLH 2.4 V 2.4 V tLHLL 0.8 V tRLRH 2.4 V
ALE
RD
2.4 V tAVLL tLLAX tLLRL tAVRL 2.4 V 0.8 V tAVDV tRLDV tRHAX 2.4 V 0.8 V tRHDX 0.8 VCC 0.8 VCC 0.8 V
A23 A16
AD15 AD00
2.4 V
2.4 V
Address
0.8 V 0.8 V 0.2 VCC
Write data
0.2 VCC
86
MB90580B Series
(6) Bus Timing (Write)
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name A23 to A16, AD15 to AD00, WRH, WRL WRH, WRL AD15 to AD00, WRH, WRL WRH, WRL, AD15 to AD00 WRH, WRL, A23 to A16 Condition Value Min. tCP - 15 3 tCP/2 - 20 3 tCP/2 - 20 20 tCP/2 - 10 tCP/2 - 15 tCP/2 - 20 Max. Unit Remarks
Parameter Effective address WRH, WRL time WRH, WRL pulse width Effective data output WRH, WRL time WRH, WRL data hold time WRH, WRL address effective time WRH, WRL ALE time WRH, WRL CLK time
Symbol
tAVWL
ns
tWLWH
ns
tDVWH
ns
tWHDX
ns
tWHAX
ns
tWHLH tWLCH
WRH, WRL, ALE WRH, WRL, CLK
ns ns
* Bus Timing (Write)
tWLCH 2.4 V
CLK
tWHLH 2.4 V
ALE
tWLWH
WRH, WRL
0.8 V
2.4 V
tAVWL 2.4 V
tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V
A23 to A16
0.8 V
AD15 to AD00
2.4 V
2.4 V
Address
0.8 V 0.8 V
Write data
0.8 V
87
MB90580B Series
(7) Ready Input Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tRYHS tRYHH Pin name RDY Condition Value Min. 45 0 Max. Unit ns ns Remarks
Parameter RDY setup time RDY hold time
Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHS
RDY (wait inserted) RDY (wait not inserted)
0.2 VCC
0.2 VCC
0.8 VCC
0.8 VCC
tRYHH
88
MB90580B Series
(8) Hold Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tXHAL tHAHV Pin name Condition HAK HAK Value Min. 30 tCP Max. tCP 2 tCP Unit ns ns Remarks
Parameter Pins in floating status HAK time HAK pin valid time
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HAK
0.8 V tXHAL
2.4 V tHAHV 2.4 V
Pins
2.4 V 0.8 V
High impedance
0.8 V
89
MB90580B Series
(9) UART0 to UART4
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK4 SCK0 to SCK4, SOT0 to SOT4 CL = 80 pF + 1 TTL for an output pin of SCK0 to SCK4, internal shift clock SIN0 to SIN4 mode SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4, CL = 80 pF + 1 TTL SOT0 to SOT4 for an output pin of external shift clock SCK0 to SCK4, mode SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 Condition Value Min. 8 tCP -80 100 60 4 tCP 4 tCP 60 60 Max. 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Note: *These are AC ratings in the CLK synchronous mode. *CL is the load capacitance value connected to pins while testing. *tCP is machine cycle time (unit:ns).
90
MB90580B Series
* Internal shift clock mode
tSCYC 2.4 V 0.8 V tSLOV 2.4 V 0.8 V
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
91
MB90580B Series
(10)Timer Input Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tTIWH tTIWL Pin name IN0 to IN3, TIN0 to TIN2 Condition Value Min. 4 tCP Max. Unit Remarks ns
Parameter Input pulse width
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(11) Timer Output Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name OUT0, OUT1, PPG0, PPG1, TOT0 to TOT2 Condition Value Min. 30 Max. Unit Remarks
Parameter
CLKTOUT transition time
tTO
ns
CLK
2.4 V
tTO
2.4 V TOUT 0.8 V
92
MB90580B Series
(12) Trigger Input Timimg
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name IRQ0 to IRQ7, ADTG Condition Value Min. 5 tCP Max. Unit ns Remarks
Parameter Input pulse width
Symbol tTRGL
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
93
MB90580B Series
(13) IEBusTM Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter TX RX delay time (rise) TX RX delay time (fall) Symbol tDLY1 tDLY2 Pin name TX, RX TX, RX Condition Value Min. 0 0 Max. 1000 1000 Unit ns ns Remarks
TX
0.7 VCC 0.3 VCC tDLY1
RX
0.7 VCC 0.3 VCC tDLY2
MB90580B series TX RX
Driver/ receiver
TX RX BUS+ BUS-
IEBusTM
94
MB90580B Series
5. A/D Converter Electrical Characteristics
(3.0 V AVRH - AVRL, VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name VOT VFST IAIN VAIN IA IAH IR IRH -- AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 Value Min. AVSS - 3.5 Typ. 10 +0.5 Max. 5.0 2.5 1.9 AVSS + 4.5 Unit bit LSB LSB LSB mV mV ns ns A V V V mA A A A LSB * * Remarks
Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling period Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels
AVRH - 6.5 AVRH - 1.5 AVRH + 1.5 AVRL AVRL + 2.7 0 176 tCP 64 tCP 5 400 10 AVRH AVCC AVRH - 2.7 5 5 4
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 5.0 V) Note: * The error increases proportionally as |AVRH - AVRL| decreases. *The output impedance of the external circuits connected to the analog inputs should be in the following range. *The output impedance of the external circuit : 15.5 k (Max.) (Sampling time = 4.0 s) *If the output impedance of the external circuit is too high, the sampling time might be insufficient.
C0
Comparator Analog input
C1
95
MB90580B Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF 3FE 3FD
Actual conversion value
0.5 LSB
Digital output
{1 LSB x (N - 1) + 0.5 LSB}
004 003 002 001 AVRL
(Measured value) Actual conversion value Theoretical characteristics
0.5 LSB AVRH
VNT
Analog input VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVRH - AVRL [V] 1024
Total error for digital output N = 1 LSB = (Theoretical value)
[LSB]
VOT(Theoretical value) = AVRL + 0.5 LSB [V] VFST(Theoretical value) = AVRH - 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
96
MB90580B Series
(Continued)
Linearity error
3FF 3FE 3FD
Differential linearity error
Theoretical characteristics
N+1 VFST (Measured value)
Actual conversion value
{1 LSB x (N - 1) + VOT }
Actual conversion value
Digital output
Digital output
N
004 003 002 001 AVRL
(measured value) Actual conversion value
VNT
V(N + 1)T N-1 VNT
(Measured value) (Measured value) Actual conversion value
AVRH
Theoretical characteristics (Measured value) VOT
AVRH
N-2
AVRL
Analog input Linearity error of = digital output N
Analog input VNT - {1 LSB x (N - 1) + VOT} 1 LSB - 1 LSB[LSB] [V] [LSB]
Differential linearity error V (N + 1) T - VNT = 1 LSB of digital output N 1 LSB = VFST - VOT 1022
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
97
MB90580B Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 7 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz)
* Equipment of analog input circuit model Analog input
C0
Comparator
C1
MB90587, MB90V580B MB90F583B MB90583B Note: Listed values must be considered as standards.
* Error
R 1.5 k, C 30 pF R 3.0 k, C 65 pF R 2.2 k, C 45 pF
The smaller the | AVRH - AVRL |, the greater the error would become relatively.
8. D/A Converter Electrical Characteristics
(VCC = AVCC = 5.0 V10%, VSS = AVSS = DVSS = 0.0 V, TA = -40 C to +85 C) Value Min. VSS + 3.0 Typ. 8 10 120 20 Max. 0.9 1.2 1.5 20 AVCC 300 10 Unit bit LSB % LSB s V A A k *2 *1 Remarks
Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance *1 : Load capacitance: 20 pF *2 : In sleep mode
Symbol Pin name IDVR IDVRS DVRH DVRH
98
MB90580B Series
s EXAMPLE CHARACTERISTICS
* Power Suppy Current of MB90F583B
ICC vs. VCC TA = 25 C, external clock input
45 40 35 30
ICC (mA)
ICCS vs. VCC TA = 25 C, external clock input
20 f = 16 MHz f = 12 MHz ICCS (mA) 10 f = 10 MHz f = 8 MHz 5 f = 4 MHz f = 2 MHz 0 2 3 4 VCC (V) 5 6
f = 16 MHz
f = 12 MHz f = 10 MHz f = 8 MHz
15
25 20 15
f = 4 MHz 10 f = 2 MHz 5 0 2 3 4 VCC (V) 5 6
ICCL vs. VCC TA = 25 C, external clock input
70 60 50
ICCL (A)
ICCLS vs. VCC TA = 25 C, external clock input
50 45 40 35 ICCLS (A) 30 25 20 15 f = 8 kHz
f = 8 kHz
40 30 20 10 0
10 5 0 2 3 4 VCC (V) 5 6
2
3
4 VCC (V)
5
30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 2
ICCT vs. VCC TA = 25 C, external clock input
6
f = 8 kHz
ICCT (A)
3
4 VCC (V)
5
6
(Continued)
99
MB90580B Series
(Continued)
VOH vs. IOH TA = 25 C, VCC = 4.5 V
1000 900 800 700 VCC - VOH (mV) 600 500 400 300 200 100 0 0 1 2 34 5 6 7 8 9 10 11 12 VOL (V) 1000 900 800 700 600 500 400 300 200 100 0 0 12 34 5 6 78 9 10 11 12 IOH (mA)
VOL vs. IOL TA = 25 C, VCC = 4.5 V
IOL (mA)
100
MB90580B Series
Power Suppy Current of MB90583B ICC vs. VCC TA = 25 C, external clock input
30 f = 16 MHz 20
ICCS vs. VCC TA = 25 C, external clock input
25 f = 12 MHz 20 ICC (mA) ICCS (mA) f = 10 MHz f = 8 MHz 15
f = 16 MHz f = 12 MHz
10
f = 10 MHz f = 8 MHz
15
10 f = 4 MHz 5 f = 2 MHz
5
f = 4 MHz f = 2 MHz
0 2 3 4 VCC (V) 5 6
0
2
3
4 VCC (V)
5
6
ICCL vs. VCC TA = 25 C, external clock input
70 60 50 40 30 20 10 0 ICCLS (A) ICCL (A) f = 8 kHz 50 45 40 35 30 25 20 15 10 5 0 2 2 3 4 VCC (V) 5 6
ICCLS vs. VCC TA = 25 C, external clock input
f = 8 kHz
3
4 VCC (V)
5
6
ICCT vs. VCC TA = 25 C, external clock input
30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 2 3 4 VCC (V) 5
f = 8 kHz
ICCT (A)
6
(Continued)
101
MB90580B Series
(Continued)
VOH vs. IOH TA = 25 C, VCC = 4.5 V
1000 900 800 700 VOL (V) 600 VCC - VOH (mV) 500 400 300 200 100 0 0 1 2 34 56 7 8 9 10 11 12 1000 900 800 700 600 500 400 300 200 100 0 0 1
VOL vs. IOL TA = 25 C, VCC = 4.5 V
2
3
4
5
6
7
8
9 10 11 12
IOH (mA)
IOL (mA)
102
MB90580B Series
s INSTRUCTIONS (351 INSTRUCTIONS)
Table 1 Item Mnemonic # ~ Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
RG B
Operation LH
AH
I S T N Z V C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
* Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles.
103
MB90580B Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
104
MB90580B Series
Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension *
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
105
MB90580B Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Listed in tables of instructions 1 2 1 1 2 2 0 0
Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (b) byte
Cycles Access
(c) word
Cycles Access
(d) long
Cycles Access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
106
MB90580B Series
Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH
I
S
T
N
Z
V
C
RMW
3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - Z Z - - - - - - - - - - - - - - - - - - - - - - -
4 2 2+ 5+ (a) 7 2 2+ 9+ (a)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
107
MB90580B Series
Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - -
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW dir, A MOVW addr16, A MOVW SP A , MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a)
2 0 0 2x (c) 4 0 2 2x (c) 2 0 0 2 0 0 (d) 0 0 (d)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
108
MB90580B Series
Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z byte (A) (A) - (ear) Z byte (A) (A) - (eam) - byte (ear) (ear) - (A) - byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
109
MB90580B Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2 2 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 7 2+ 9+ (a) 2 7 2+ 9+ (a)
2 0 2 0 2 0 2 0 4 0 4 0
0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 0 0 1 0 0 2 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
110
MB90580B Series
Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Operation
Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (eam)
LH AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam) 0 long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
111
MB90580B Series
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5
RG
Mnemonic DIV DIV DIV DIVW DIVW A A, ear
B 0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
A, eam 2 + A, ear A, eam 2 2+
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
Z Z Z - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4:
A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 +
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
112
MB90580B Series
Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b)
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
113
MB90580B Series
Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH
AH
I
S
T
N
Z
V
C
RMW
0 2 0 0 2 0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2+ 5+ (a) 1 2
0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2+ 5+ (a)
0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
114
MB90580B Series
Table 18 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
# 2 2
~ 2 2
B 0 0
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit)
LH AH
I
S
T
N
Z
V
C
RMW
0 0
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
* * * * * * * * *
* * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
--* --* ---
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
--*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * *
long (A) Arithmetic right shift (A, R0) -
- -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
115
MB90580B Series
Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0
LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2)
2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6
(c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
116
MB90580B Series
Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE
CBNE
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
# 3 4
10
~ * *1 *2 *3 *4 *3 *5
1
RG
0 0 1 0 1 0 2
- - - - - - - - - - - - - - - -
----* ----* - - - - - - - - - - - - - - - - * * * *
* * * * * * * * * * - - - - *
* * * * * *
* * * * * *
- - - - - - - * - * - - - - - -
ear, #imm8, rel
eam, #imm8, rel*
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
4 4+ 5 5+ 3
DBNZ DBNZ
ear, rel eam, rel
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
----* ----* ----* ----* - - - - - R R R R * S S S S * - - - - * - - - - *
*- *- *- *- - - - - * - - - - *
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#imm8
--------
UNLINK RET *8 RETP *9
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
-------- -------- --------
- - -
*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
117
MB90580B Series
Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH
I
S
T
N
Z
V
C
RMW
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - -
- - - - * - - - - - - - - - - * * - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * *
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space
- - - - - - - -
------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - -
Z* -- - - - - - - - - - - - - - -
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 x (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
118
MB90580B Series
Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *5 *5 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
119
MB90580B Series
Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG
B * *3 *4 *4 *3 *6 *6 *7 *7 *6
3
* *5 *5 *5
5
Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
MB90580B Series
s ORDERING INFORMATION
Part number MB90F583BPFV MB90583BPFV MB90587PFV MB90F583BPF MB90583BPF MB90587PF Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) Remarks
121
MB90580B Series
s PACKAGE DIMENSIONS
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007 -.001
+0.08 +.003
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
2000 FUJITSU LIMITED F100007S-2C-4
Dimensions in mm (inches)
Note : The external dimensions show here are for reference only. For official dimensions, contact a FUJITSU representative.
122
MB90580B Series
100-pin plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
2000 FUJITSU LIMITED F100008-3C-3
Dimensions in mm (inches)
Note : The external dimensions show here are for reference only. For official dimensions, contact a FUJITSU representative.
123
MB90580B Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0010 (c) FUJITSU LIMITED Printed in Japan

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